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a video on MOESI please

Only (b) is deadlock-free.

Gracias thanks

Really appreciate the clear & concise way this was presented.

Hi, there is typo on 5:43, when a P1 is in state Sm, and it snooped a BusRd, it doesn't update the main memory, only P3. But top-left of the screen, it says P1 flushes, sending update to P3 and main memory.

There is a typo/mistake at 2:00, it says that "if there is a cpu write miss and the shared line is asserted, the changes is written through to main memory, and the block is cached in state D." According to the diagram, in this case, the block will be cached in S, not D.

great explanation

This is fantastic. Thanks for posting.

In 6:40, why W(x)1 is not causally related to R(x)1, as you said before? does not make sense.

Thanks for the video! It helped tremendously in understanding multilevel cache policies!

From E to S and I, when BusRd or BusRdx occurs, why Flush is needed. Can't requesting processor directly read it from main memory?

the best video explaining MSI, thank you

The part about writes not reaching all processes instantly was what I was missing. Thanks

pRDON DA BEN MATLAB GÖRMÜYORUM GERİZEKALI DEVREDE GÖSTERSENE

Perfect Presentation

So clear Explanation.Thanks a lot !!!

Nice, finally understood causal consistency!

Great explanation! Thank you :)

great explanation

Your voice sounded so familiar, and today I figured it out, it's the AI in 2001 space odyssey.

Thanks

Please upload more lectures

Awesome lecture professor. Thanks from india

what does "BusRdX" mean?

Thank you for the explanation

Hi, just wanted to say that this was really usefull and well explained. Thanks

Thank you so much. This is the only good explanation of release consistency that I could find on TH-cam.

Good video, that helped a lot!