วีดีโอ

This is close maybe th-cam.com/video/dX9CGRZwD-w/w-d-xo.htmlsi=KZCEnoho9Ryhy04j

I'm guessing from his initial disclaimer that he's not giving away trade secrets.

@@MikeDrop136 I meant it would be nice to hear a bit more of the story behind getting permission.

@@choggi Permission from who?

I would imagine he's signed one or two NDAs, and while he's talking about publicly available info. I could see some suits saying hello to their lawyers if he didn't ask beforehand.

Everything they said is very much public information

It's not far from 35:00 14nm "Toshiba DRAM" at least for Intel, and 7,5,3nm are basically still variation of these 14nm stuff, distances between fins are still quite large ~50-40nm i lost touch when AMD Ryzen came out there is some progress but now it's more of optimizing costs. And putting more layers stack these on top of each other. Make masks for product it takes ~500mln masks are difused as well and there are dozens different layers multiple steps. If US continue to push war against China / Taiwan we might have more time to catch up ;)

​@@KabelkowyJoe2023 😳

​@@preysan What? We are stuck (most compenies) at exact same tech in 2023 as we had 2010-2013. Let me explain why and what changed what not (what i know). For regular planar transistor minimum size is 28nm. Both bulk and SOI (silicon on insulator) there was attempt to make 22nm but size of gate is too small and parameters of such transistors was not optimal. It's highly optimized even using 192nm light few steps, masks. I don't know precisely but let's say 30 steps, 1month to make chip. So cheap transistors are 28nm bulk, 32nm SOI just like we had in 2010. Still used to make microcontrollers and stuff. To make 22nm,14nm, 12nm FinFETs both Intel, TSMC, GF and Samsung used 192nm light. But transistor is vertical and it takes 100 masks to manufacture let's say 3 months to make single wafer of chips. I heard it takes total 8months from final desing in EDA /CAD to real chip - because of how complicated it become. Some companies including Chinease SMIC tried to make 10nm, 7nm, 5nm using 192nm light it takes anormous number of masks all have to be calculated it takes months on GPU powered math centers then takes months to make. To prepare manufacturing of single design they say it cost 500mln dolar alon. In FLASH memory and RAM main progress was to put on layers on top of each other. We are now making 128x layers. Intel and Micron - Optane tried to make as much in one process others are stacking like sandwitches. RAM im not sure what is now but not long time ago was made 19nm then 14nm it's technology. So basically what was shown on presentation. STACKING allowed us to have more and more capacity. When it comes to AMD they are able to cut costs by mixing processes. Still making some chips 14nm, 12nm while cores are 5nm 4nm but these are possible thanks to TSMC cooperation with ZEISS German and ASML - Dutch to finally create EUV 10nm light based machine. It's revolution, exceptional revolution took 20 years actually to finally replace 192nm UV. You can't use same chemicals, and vacum makes lot of problems. And thanks for that was possible to make distance between transistors smaller - smaller than 50nm wide, 100nm long and this is how they managed to pack more and more. Not by making transistors smaller but mostly making distances between transistors smaller. There are attempts to make GaaFET probably 2,3,4nm are made such way. Almost like FinFET but not solid vertical but split in 3 parts. As you could see on presentation. RAM - 80% of surface of RAM is actually analog all these voltage pumps regulators ,interfaces. Less and less it's memory itself but even if it needs good insulation and size to hold charge. What changed - we are STACKING LAYERS one on top of other. Or puting small chips on top of interposer or thin PCB and connect together like never before. I know NVidia made huge chips around 19bln transistors or so. But that is rare - possible mosly thanks to ASML EUV 10nm and TSMC. Intel struggled to make such technolgoy for decade they stuk 14nm for years trying to make 10nm cheap using 192nm light instead. But that cost them tons of money. Chinese SIMC was sanctioned - they cannot purchase ASML machines.USA sanctioned China. SMIC managed to make 14nm and even 5nm using 192nm UV but imagine 150x masks vs 30x masks it 5x more time and costs. So they abandoned will focus to increase capacity old bulk plain MOSFET transistors on 28nm. They have lot of clients. Chips are mass produced in 28nm. Some chips still made 40nm, 65nm and bigger. High power electronics can't be made small would be waste of money to use 28nm machinery. So most companies some in India are using for example old 65,90nm - 15-20 years old. Chips are smaller, indeed NVidia, Apple, AMD are capable to waste 1bln dolar on new design, but small companies stuck in 2010. I remember Buldozer was made 32nm SOI just like last IBM PowerPC's and AMD LLano was 28nm bulk. It's still in use. Era of Moore's Law from perspective of entire industry was over around 2010. It is no longer less and less expensive to make step forward. So most companies stuck in 2010. Some are letting 14nm GF and TSMC is making these. Exceptions 7,5,4nm are huge companies capable to move forward AMD, NVIdia. This is why IMO presenation pretty much describes current reality. Sorry i had to - this is how i see it :D

@@KabelkowyJoe Holy shit 🤣, Bro If you want to say something, just do it

@@KabelkowyJoe I took time to read it, but thanks a lot

When?

"All chips are analog" can really confuse people.

Well there's a "DIGITAL" badge across the grill of my bookshelf stereo speakers so they must be digital, right...😆

By the time they got to what they called "14 nm ++++", it actually was more like an 10 nm process. It's just that Intel, in a great move of anti-marketing, insisted on being honest and saying that it was just a four-times improved version of their original 14 nm process rather than an entirely novel process. The problem was the lack of architectural improvements - they basically released 5 generations of Skylake.

Those numbers were overly simplified and never told the whole story anyway.

Oh *Operating Room.* I was reading OR as in logical ||or (like instead of &&and). Interesting comment, thx!

That's what happens when common folks are 'entitled/take for granted' sophisticated technology. Technology should be privileged for scientific minded people who are watching this video.

​@@demoncloud6147let people enjoy their cat videos! It is possible to enjoy both, like i do.

they do, otherwise they wouldn't exist... all you have to do is use google for 30 seconds and find out intel has a net income of 21 billion dollars in 2019

@@r3d0c So what? That doesn't automatically mean that they make money on consumer grade products, and certainly doesn't preclude them from existence. The majority of that 21 billion dollar net income very probably comes from enterprise products (like servers, licensing agreements, etc). These types of things cost tens of thousands of dollars per unit. Inflating these prices would allow consumer grade processors to be manufactured and sold at a very slim margin.

...and I'm watching this on a computer where CPU is on a 7nm architecture.

@@TheBatracho and I'm watching this after IBM announced they have invented 2nm chips...

@@leezhieng To be fair, neither 7nm nor 2nm actually have 7nm or 2nm transistors, respectively. It became an "as-if" measure as the actual 3D structure of the transistors and the gates they build got a bit too complicated for marketing :) Nowadays, x nm refers to a peak transistor density (yay marketing), rather than actual feature size - and even that's a marketing lie. The next time you think about why Intel's fabs are "so behind" the cutting edge in nanometers, that's part of the reason. For example, Intel's 10nm chips actually have a higher peak density than TSMC's 7nm chips, and twice as much as Samsung's 10nm chips. The IBM 2nm chip? You might expect three to nine times the density if you assumed it refers to the size of the transistors or minimum feature size or something. In reality, the peak transistor density is only 40% higher than Intel's 7nm. Just like back in the day, comparing chips from different manufacturers based on their listed characteristics (like TDP, clock rate, "nm"...) is essentially pointless. And then you learn that Intel is backporting its 10nm architectures to 14nm for... reasons. Chip making is complicated. Even without MBAs in engineering roles and retarded marketing.

Daaang you are proper smart AF.. impressive. I should have stayed in school.. well I guess I missed the smart train.