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AnalogVLSI
เข้าร่วมเมื่อ 12 เม.ย. 2008
ChatGPT for Digital Verilog and Analog Verilog-A
How can we use chatGPT by Open AI for the VLSI simulation and testing? We generate Verilog models, testbench and also take a look at Verilog-A modeling
มุมมอง: 1 709
วีดีโอ
Cadence Maestro/ADE XL Tutorial: Create multiple testbench in one view
มุมมอง 2.4Kปีที่แล้ว
Create multiple test benches for a block in a Maestro/ADEXL view. You can use this to simulate various schematics with corresponding tests in one view
DC operating point analysis on Cadence
มุมมอง 2.7Kปีที่แล้ว
Hi I go through DC operating point analysis on Cadence. We use annotations for op points. Happy learning!
Could you please make the other video on ConfigView? I really look forward to seeing that! Thank you~
How is this open loop gain ? it is closed loop gain
Thank you
This video is helpful. I've learned a lot. Thank you!
create a ai chip to run an llm
hello sir , i want to do verilog A code for some Equations so please let mwe know how to do it.
Thanks
Amazing 👌