Digital IC/FPGA Design P3: Common Used Hardware Architectures
a big step towards complex IP design
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In this chapter I will introduce common used hardware architectures, including:
1: Behavior of SRAM and usage suggestions;
2: Handshake interface and synchronous FIFO;
3: Pipeline to maximal clock frequency;
4: Arbiter;
5: Cross clock domain (CDC) and asynchronous FIFO;
6: Ping-Pong;
7: Pipeline with control (feedback);
8: Pipeline with hazard and forward path;
9: Slide window;
These are useful architectures engineer used to deal with complex designs, such as RISC-V CPU core, AI accelerator and so on. To help you mastering them, I will assign a coding exercise after each section.