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I do not care if US is subsidizing Intel or China is subsidizing Huawei is not my bussines, i have other concearns I have my family to take care of and my invention. If you want to fight for your hegemony, just keep doing that but I am not part of it. Note: Do not dare to call an inventor a bullshiter, I am not a politician or member of political party, pay intention to this title, you must be with schizophrenia disease.

To be honest, systemverilog becomes very interesting when we use classes. But that part falls under systemverilog for verification.

I did a course on systemverilog from doulos. Definitely recommended.

Here in Europe, people really don't use verilog and systemverilog

Thank you for teaching so eloquently. As a current NCSU student, my goal is to conduct research in VLSI, ASIC design, and verification.

Good work!

if you use switch cases or if statements the cpu will take more time figuring out whether the imposed condition is true or false, i am fairly new to verilog but i've learnt C, embedded C and assembly, so i was wondering, can you use decoders or encoders instead of MUXs and DEMUXs in order to avoid conditional statements?

Does anybody care what these high frequencies are doing to the human brain?

thank you

So the gate all around is not 2 nanometers. The footprint is forty nanometers size. Thats a bit misleading.

*promo sm* ❤️

The 2d material will be atomeras mst.

Great video professor , can u make a video on the best profile for bachelor student who wants to study phd in Computer Engineering in NCSU ? Thanks

The Saturn V vs A100 is facetious. They are not of the same era and the rocket industry also has a massive investment. The A100 transistors are mostly identical parts in highly regular arrays , made in one sequence under tight control of a single firm. The complexity of integration of a rocket is its own problem.

Where can I find the lecture slides for the video? Thanks

finally a normal English

Thank you very much

If the two clocks are source from the same PLL do we still need an asynchronous FIFO or a simple shift register would be enough?

Don't waste your time or money. Indian Mafia controls STEM now.

atomera mst

Good fucken video thank you sir

There's another way to implement the foo function. You can also do it like this: always @(a or b or c) case (a) 0 : foo = b | c; 1 : foo = b ^ c;

Is this course completed?

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"When the two clocks are "Roughly" the same" What do you mean by this?

Lots of questions but this was very useful. Thank you.

I need to come back to this once I understand what kind of assignment that is ( <= ) and what the difference is between the two types ( <= vs = ). I've read it, somewhere, a while ago, but I don't know enough about Verilog and FPGAs to recall it. From that point in the video onwards, I was just distracted by not knowing what it meant.

Thanks for sharing ✨✨✨

Fantastic summary, keep the videos coming!

Which type of design does a bitcoin miner ASIC use? Full custom, standard cell or gate array design?

Would love to learn about ASIC chip design from NCSU, but I'm a business graduate student though, would I get admission in this course?

This cleared up a week's worth of confusion, thank you!!

Very good to see you after a long time. One request : can you upload a complete course on pure verification? Or may be ic layout?

if u could please bring back the old playlist it really helps a lot of ECE students who are struggling with the subject or students whom may be living in countries where the education level is poor which i consider myself one of them and this playlist is really one of the very few sources that we have on the subject of digital ASIC design so if you could kindly bring it back or reupload it it would be greatly appreciated ,thanks in advance

90% of videos turned in "private video"

I can't access all the videos of the playlist

Good explanation. Ummm ... at 2:02, 10+7 should be 0b1010 + 0b0111 = 0b0001 c=1, rather than 0b1100 + 0b0111 = 0b0000 c=1.

there is some error with d latch structure, can you please confirm?

When we implement Asynchronous/Synchronous FIFO, What timing design constraints do we need?

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how can we apply for a PHD in NC uni. ,,?

1 is neither prime nor composite. 2 is prime.

Thanks!

Thanks!

Thank you very nice video

th-cam.com/video/TkoGMZXBcG4/w-d-xo.html verilog understading in the simplest way that i have seen

Don't get a PhD in engineering unless you really have a passion to pursue R&D efforts in your career (or for whatever reason your company wants you to pursue it and is paying for it). It's practically useless otherwise.

please show reference links

Can't afford conventional circuit simulators? study androidcircuitsolver on google