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please help us with more videos on SystemVerilog. And please suggest if you have any reference book for practicing this language with examples for beginners. Thank you

needed 💯

can you please upload videos quickly so, i can complete whole system verilog ..please

at 3:24, for me its getting # KERNEL: on.sum = 1 # KERNEL: summ = 1 implemented in EDA playground via a simulator "Aldec Riviera pro 2023.04"

sir can you share notes plx mera exam december mai hai

Nice

Hi :) I recently started my journey into the design verification world. I got a job where I will be doing SystemVerilog for testbench in UVM (for ASICs), I was wondering if you have any tips so I can learn faster, so that I can go to big companies in 2/3 years?

Great explanation bhaiya! This OOP video was exactly what I needed. Please make videos on other System Verilog topics too.

OOP in System Verilog finally makes sense after watching this video series

This tutorial makes OOP concepts so clear. Thanks a lot!

You explained inheritance and polymorphism perfectly🤩

I’ve been struggling with OOP, but this video made it so simple! thank you.

The examples you used made OOP much easier to understand.

Fantastic breakdown of classes and objects in System Verilog!

Great explanation of OOP in System Verilog! Very helpful.

Awesome start to the channel! Excited for more advanced topics bhaiya

You make complex topics so easy to understand. you're doing great job!

Loving the clarity and depth of your explanations. Keep it up bhaiya👍👍

This tutorial is a lifesaver for understanding System Verilog🙏Thank you

Your teaching style is awesome! This is super helpful for my learning SV.

Perfect breakdown of the basics bhaiya😀 Can't wait for more videos!"

Amazing content for anyone starting with System Verilog. Subscribed💪

Clear and concise explanation👍 Thanks for making this easy to follow🙏🙏

Really helpful tutorial for beginners. Keep up the good work!

Great intro to System Verilog! Looking forward to more content💯🔥

Nice explanation about super keyword bhaiya waiting for more videos

bhaiya add more videos on system verilog. you are doing good. really enjoyed the video.

Please speak English brother ww don't hindi Or add subtitles in English

Sir any plan about starting UVM?

sir,what ever the memory created for objects class1 and class2 stays till end of simulation time?

I have checked, i think code is correct, it can be a simulator issue, you can try running it on EDA playground. module argument_passing; int x,y,z; //function to add two integer numbers. function int sum(ref int x,y); x = x+y; return x+y; endfunction initial begin x = 20; y = 30; z = sum(x,y); $display("-----------------------------------------------------------------"); $display("\tValue of x = %0d",x); $display("\tValue of y = %0d",y); $display("\tValue of z = %0d",z); $display("-----------------------------------------------------------------"); end endmodule

sir in pas by ref code function should be automatic........ I simulate the code and without declaring automatic output not come. You please check once.

very well explained sir. but sir apka likhe point padne me nahi aa rahe. jyada hi cursive ho gyi h

very well explained sir

very nice explanation and i really enjoyed it .