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Srisa Medicharla
เข้าร่วมเมื่อ 3 มี.ค. 2022
CMOS Inverter || Post Layout Simulation with Long Wire
CMOS Inverter || Post Layout Simulation with Long Wire
มุมมอง: 438
วีดีโอ
CMOS Inverter || Parasitic Extraction and Post-Layout Simulation
มุมมอง 7K2 ปีที่แล้ว
This is a video on the post-layout parasitic extraction and simulation of a CMOS Inverter.
Invoking Assura Tool
มุมมอง 1.6K2 ปีที่แล้ว
This includes the series of steps needed to invoke the Assura-Quantus menu for Layout DRC and LVS checks.
CMOS Inverter || Testbench and Simulation
มุมมอง 1.2K2 ปีที่แล้ว
In this video, a test bench schematic has been built for an inverter on Cadence Virtuoso and simulated to test its working.
CMOS Inverter || Schematic Design and Symbol Creation
มุมมอง 7062 ปีที่แล้ว
This is a video tutorial on how to design the schematic and symbol of a CMOS inverter on Cadence Virtuoso EDA tool.
Invoking Cadence Virtuoso
มุมมอง 6672 ปีที่แล้ว
This video contains information on how to login to your individual directories on Hawking/Einstein server and open Cadence Virtuoso tool.
Installation of GlobalProtect VPN & MobaXterm
มุมมอง 4192 ปีที่แล้ว
This video guide explains how to setup GlobalProtect VPN and MobaXterm application.
Please share the canvas and files
can you help me why assura not showing in my window..
Hi, I am follwing the same procedure. When I set the output as spice the quantus runs with no error. but when I use extracted view it gives me an error saying that there is no library cell mapping file like extview.trp (V2), or icellmapfile. yaml or extview.rul. Do you know where i can find those?
Where is canvas mam
At 4:38 you needed to set one of the views to av_extracted. Otherwise it doesn't know to use the post-layout view, and will default to the base model. That model does have some parasitics built in, which is probably why you're seeing that delay at 6:38. Try changing to av_extracted and see if that delay doesn't increase