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PLL infact generates jitter, how is it used for noise cancellation

Best content for PLL

Very nice sir

thank you soo much

🫡

Doing just the maths will save us from ambiguity regarding with impedance reflection concept... Thanks... 🙏🏾🙏🏾For guys having the problem with the concept just do the algebra carefully then finaly you will arrive at your Rin Rout Av Ai

This content is best on the internet for learning PLL.

The content is the best i found on the Internet.... Keep uploading such a videos 😊❤

can you tell me why assura tab not showing in my cadnece....

hello sir, I have specific parameters for MOSFET, which need to be simulated in LTSPICE. But a MOSFET with similar parameters is not available in LTSPICE. I need your help. please consider sir.

Sir, can I derive the equation for Av like this? I think it's wrong, but I don't know what the error is. vo=-βibRc；vin=ieRE=(1+β)ibRE；Av=vo/vi=-β/(1+β)×Rc/RE。

Appreciable

Very good explanation for those want to understand the underline reasons. Thanks !

Sir, please continue the series. Please teach current mirrors and differential amplifiers . No other TH-cam channel provides this level of detail on these circuits.

Thank you very much

cannot access PTM 65nm website

Excellent explanation..Thank you

could you help me to measure Cg Cd Cs of Nmos and Pmos in Ltspice?

Excellent video! You are a great teacher!

LK

Hats off to you.Clear all doubts

sir tutorial..?

sir when will you please upload the other lectures of this series.

LT spice is open source

Sir can you share your email.

Very helpful content, thanks we expect more quality content like this

This is best explanation of Transmission Gate and WEAK 0 and weak 1

Could not open the saved file

Great explanation. Thank you :)

It's very useful,thanks Dr. I would like to ask you, sir Why most of designer or researchers use 180nm when they design LDO ??? Thanks

Very informative presentation.

190nm not working

It's a wonderful and very useful presentation. Thank You

I am not getting the result and the error is "the cell view has been modified since the last extraction error validate"

Great job. People like you make the world go around! Thank you!

th-cam.com/video/sGxNE6UgkeE/w-d-xo.html

Hello I could not install the HSPICE on my computer, for that, if possible help me, I send you the PTM files (predect technology model) and you draw me the output and transfer characterizations of a 10 nm FinFET with the HSPICE software, here is my email address: sciencephysique.dz@gmail.com

Glade is an open Source Software; GLADE Tutorial | CMOS Inverter Layout 1 th-cam.com/video/Qr0nTPo-Ri0/w-d-xo.html

Thanks a lot!

Great tutorial! Thank you!

Very detailed tutorials, Thanks!

Excellent tutorial. Thank you very much for sharing.

plz upload more videos like this it will be helpful for beginner like me. Thank you

Hi sir, When i do the RC extraction using PEX .. while loading pex.tec file i get the following error " undefined layer name parameter:NSD_C" can you suggest a method to overcome this error??

Thanks a lot. Really useful video.

Layout design and post-layout simulation using HSPICE (Part-2)? Please share the link.

That's what I was looking for everywhere. Finally here it is!! Thanks a lot